Forward error correction with configurable latency

ABSTRACT

A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.

CROSS-REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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REFERENCE TO A SEQUENCE LISTING, A TABLE, OR A COMPUTER PROGRAM LISTINGCOMPACT DISC APPENDIX

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BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention discloses a method of performing forward errorcorrection with a configurable latency for digital communicationssystems.

2. Background of the Invention

Long-distance digital communication systems, such as optical submarinecable systems, are responsible for the transmission of significantamounts of data. This data is transmitted across great distances, oftenfrom continent to continent. During transmission, data can becomecorrupted from noise within transmission channels, faults intransmission or receiving devices, or data errors from reading from andwriting to an elastic store. Therefore, Forward Error Correction (FEC)is employed to minimize the error probability of transmitted data.

Claude Shannon first suggested a maximum possible channel throughoutwhich developed into a theorem of error correction describing theaddition of redundant data to payload data for the correction of errorsfrom channel noise or interference during transmission. This FECincreases the reliability of transmitted data by encoding a block ofpayload data with redundant data bits through an algorithm generated atthe transmitter, which allows a decoder to determine if an error hasoccurred. The decoder employs the code generated by the encoder toidentify what information, if any, has been corrupted by noise orinterference during transmission, and the decoder can in turn correctthese errors.

Typically, a FEC system architecture provides a fixed latency system,meaning that the architecture could be limited to the type of dataapplication it can be utilized with. To allow the system to adapt foruse with various data applications, a method of providing a configurablelatency FEC is required.

SUMMARY OF THE INVENTION

The present invention discloses a method of performing forward errorcorrection with configurable latency, where a configurable latencyalgorithm evaluates a target Bit Error Rate (BER) against an actual BERand adjusts the size of a configurable buffer such that the target BERmay be achieved when utilizing the smallest buffer size possible.

The configurable latency algorithm begins by utilizing the maximumnumber of available buffer locations within the configurable buffer toachieve the target BER. When errors are corrected without theutilization of each of the configurable buffer locations, the algorithmreduces the size of the buffer by y buffer locations; the algorithm maycontinue to successively reduce the size of said buffer until theminimum number of buffer locations are utilized to achieve the targetBER. If the buffer locations have been reduced such that the buffer sizeis too small and the target BER cannot be achieved, the algorithm mayincrease the size of the buffer until the minimum number of bufferlocations are utilized to achieve the target BER.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of the architecture of the presentinvention.

FIG. 2 illustrates a block diagram of an illustrative embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 depicts an illustrative embodiment of the present invention,whereby configurable buffer (22) is set to utilize the maximum number ofbuffer locations. For exemplary purposes, FIG. 2 illustratesconfigurable buffer (22) with 16 buffer locations, labeled 0-15.Itshould be noted that FIG. 2 is provided for exemplary purposes and isnot meant to limit the scope of the invention, as any size buffer may beutilized. As illustrated in FIG. 1, input data (20) is transmitted intothe system and written into configurable buffer (22), FEC block (24) andalgorithmic logic block (28), where algorithmic logic block (28)represents the configurable latency algorithm. Data input (20) includesa target BER; when given this Target BER, the algorithmic logic block(28) starts by utilizing the maximum number of configurable buffer (22)locations to achieve the target BER.

As data is input to the system, FEC block (24) is able to act upon thedata as it is transmitted through configurable buffer (22). Asillustrated, data corrected by FEC block (24) is output fromconfigurable buffer (22) into error monitor (26). Error monitor (26)evaluates the actual BER and inputs the actual BER into algorithmiclogic block (28), allowing algorithmic logic block (28) to compare thetarget BER and actual BER such that the algorithmic logic block (28).The configurable latency algorithm of algorithmic logic block (28) isnow able to determine the amount of buffer locations and the amount oflatency required to output the correct BER and can effectively conFIG.the number of locations required in configurable buffer (22).

If the data travels through configurable buffer (22) such that thetarget BER is achieved without utilizing each of the configurable buffer(22) locations, the configurable latency algorithm of algorithmic logicblock (28) reduces the number of configurable buffer (22) locationsutilized by x and begins the process again. This process is repeated toreduce the number of locations of configurable buffer (22) to theminimum buffer size. Once errors occur, or the data travelling throughconfigurable buffer (22) cannot achieve the target BER, the configurablelatency algorithm increases the number of locations of configurablebuffer (22) by y. It should be noted that x does not have to be the samevalue as y.

An illustrative embodiment of the present invention employs FEC in theform of a Bose Ray-Chaudhuri (BCH) (1023, 993) parent code, shortened toBCH (1000, 970). BCH codes are cyclic, error-correcting, digital codesof variable lengths which are able to correct errors in transmitteddata. BCH codes typically employ a polynomial over a finite field, and aBCH codeword consists of a polynomial that is a multiple of thegenerator polynomial. The illustrative embodiment of the presentinvention operates on an m=10 Galois field with a t=3 value, where trepresents the number of errors that can be corrected within a row codeor a column code. It should be noted that this example is provided forillustrative purposes only and is not meant to limit the scope of theinvention, as other FEC codes may be utilized.

By utilizing this configurable latency architecture, the same FECarchitecture can be adapted for use across communication channels ofvarying BERs, while still maintaining data integrity. Such adaptabilityis desirable where the same architecture can be adapted for use withvarious data applications.

We claim:
 1. A method of performing forward error correction withconfigurable latency, comprising: (a) a plurality of data input to atransmission system, wherein said data includes a target bit error rate;(b) a configurable size buffer with a plurality of buffer locations,wherein a forward error correction code corrects said data as said datais transmitted through said buffer; (c) an error monitor to evaluate anactual bit error rate of said data output from said configurable sizebuffer; and (d) a configurable latency algorithm, wherein said algorithmbegins by utilizing the maximum number of available buffer locations toachieve said target bit error rate, and said algorithm then reduces thesize of said buffer by y buffer locations when errors are correctedwithout the utilization of each of said buffer locations, whereby saidalgorithm may continue to successively reduce the size of said bufferuntil the minimum number of said buffer locations are utilized toachieve said target bit error rate or, where said buffer locations havebeen reduced such that said buffer size is too small and said target biterror rate cannot be achieved, said algorithm may increase the size ofsaid buffer until the minimum number of said buffer locations areutilized to achieve said target bit error rate.
 2. The method of claim1, wherein said forward error correction code is a Bose Ray-Chaudhuri(BCH) code.
 3. The method of claim 2, wherein said Bose Ray-Chaudhuri(BCH) code is a BCH (1023, 993) parent code, shortened to a BCH (1000,970) code.
 4. The method of claim 1, wherein x=y or x≠y.